LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PacketSizer IS
   PORT(
        srcPort : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        buffer0, buffer1, buffer2, buffer3 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		output : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
       );
END PacketSizer;

ARCHITECTURE packetsizer_arch OF PacketSizer IS

COMPONENT MUX11bit4way IS
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		data2x		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		data3x		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
END COMPONENT;

BEGIN

Ramirez : MUX11bit4way PORT MAP (buffer0, buffer1, buffer2, buffer3, srcPort, output);

   
END packetsizer_arch;